1. Field of the Invention
This invention relates to the field of circuit design. In particular, the invention relates to a circuit and method for maintaining the configuration process in a mask programmed integrated circuit implementation of a circuit design for a programmable logic device.
2. Description of the Related Art
Programmable Logic Devices (PLDs) allow circuit designers to program the PLDs to perform the function of a particular circuit design. Examples of programmable logic devices are Field Programmable Gate Arrays (FPGAs) and Erasable Programmable Logic Devices (EPLDs).
Random Access Memory (RAM) based PLDs use a configuration process to allow a programming circuit to program the PLD to perform the function of a particular circuit design. Non-RAM based PLDs use a similar configuration process. The configuration process uses serial and/or parallel communications between a programming circuit and the PLD. Thus, a configuration timing relationship and a configuration protocol relationship exist between the PLD and the programming circuit. This configuration timing relationship is the time from when power is applied to the PLD to immediately before the PLD is ready to function as the particular circuit design. The configuration protocol relationship is the signalling convention used between the programming circuit and the PLD during the configuration of the PLD.
In an XC4000.TM. FPGA PLD from Xilinx, Inc., of San Jose, Calif., the configuration mechanism begins after the power supply has reached a certain level (e.g., 3.5 volts). The power reaching a specified level then triggers a specific set of phases. The 1994 Xilinx Data Book, page 2-25 through page 2-31, describes the configuration process for the XC4000 FPGA product family.
In some cases, where the economies of scale warrant, a designer will want to target a circuit design for a different implementation technology. That is, a designer will want to convert a circuit design in a technology (e.g., mask programmed integrated circuit technology) other than in a programmable logic device. A Mask Programmed Integrated Circuit (MPIC) version reduces the silicon area needed to implement the circuit design and is therefore less expensive. This conversion process may be to a simple mask programmed version of the PLD, or a totally different representation; but the user logic functionality is maintained. One example of such a process is described in U.S. Pat. No. 5,550,839 which issued Aug. 27, 1996, entitled, "Mask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arrays."
A MPIC of a PLD does not have a configuration timing relationship nor a configuration protocol relationship because the MPIC is already configured and therefore already programmed. In contrast, the PLD must complete the entire configuration process prior to the commencement of the functional operation of the particular circuit design.
Therefore, one of the problems encountered by designers who convert their circuit designs to another technology is that the configuration timing relationship is not the same for the target technology. A second problem is that the configuration protocol relationship is not maintained. While these two problems may not affect the PLD's circuit design implementation logic functionality, they do affect the integration of the MPIC into the system. If the configuration timing relationship is not maintained, system problems may result that must be solved prior to the introduction of the mask programmed version into the final system. Further, if the configuration protocol relationship is not maintained, the entire system may not become operational. For example, the designer may have to alter the programming circuit or the software that executes in the system. A designer may not want to modify any other part of the system to migrate to a new target technology because this adds additional costs to the design process. The modification of the system may also add to the time it takes to release the system to the market using the target technology. The modification introduces the possibility of design mistakes into the system.
One partial solution to the configuration timing relationship problem is to include a power-on reset circuit in the target technology integrated circuit, thereby ensuring that the integrated circuit will be held in a reset state for a period of time until after the applied power becomes stable. This mechanism is referred to as "Power-On-Reset" (POR). However, the POR circuit does not completely solve the problem because the system using the target technology will still have to fully support the remainder of the configuration timing and configuration protocol relationships. If the system was not originally designed to, or is not capable of, supporting POR then the system will have to be redesigned for the target technology.
Xilinx, Inc. produces the XC4300 HardWire.TM. integrated circuit which supports an alternative configuration mechanism referenced as "Instant-On." This mechanism is documented in the Xilinx HardWire Data Book, page 2-23 through 2-25, 1994. However, the instant-on feature largely ignores the issues of the configuration protocol relationships.
Therefore, what is needed is a better solution to both the configuration timing relationship problem and the configuration protocol relationship problem. The solution should reduce, or even remove, the need to redesign the rest of the system.